Abstract

This dissertation represents the considerations of the problem of performing arithmetic operations in hardware implementations of global illumination algorithms in reprogrammable logic. The considered operations are mainly limited to multiplication and addition. The operations are performed with residue arithmetic what allows to increase performance. The new structure of residue arithmetic units for Field Programmable Gate Arrays is proposed. The main advantage of the new structure is reduced area and high speed, especially for medium and large moduli. The algorithm for designing units with specified area and delay is given as well. The new class of Hierarchical Residue Number System (HRNS) is developed. The new class enables to use small moduli in arithmetic units and to simplify the converters between residue and fixed-radix number system. The new algorithm for the sign detection of a number in three-moduli Residue Number System (RNS) is presented. The proposed method results in the fastest and the smallest circuit for sign detection. Additionally the architecture of digital processor for global illumination algorithms is developed. The architecture enables to use RNS in calculations. The use of RNS causes clock frequency and performance increase. The theoretical results are verified with practical experiments. Also, the implementation of important operations in global illumination algorithms with the designed residue arithmetic units and the new class of HRNS is presented.