Abstract

Multi-carrier modulation (OFDM), iterative error-correction-coding (Turbo and LDPC codes) have potential for enabling high capacity data-centric reliable wireless network. However, multiple-input multiple-output (MIMO), the most significant technical breakthroughs in modern communications, has shown the most profound effect on the capacity and reliability of wireless networks.

The performance improvements resulting from MIMO come at the cost of increased computational complexity and power consumption in the wireless receiver. Owing to the requirements of the portable mobile devices, the design of high throughput system with lower complexity and power is one of the key challenges in MIMO receiver design. Currently available DSP processors lack the capability to achieve such conflicting and stringent requirements. The largest potential for complexity and power reduction of highest-performance VLSI circuits for MIMO receiver lies in the joint optimization of algorithms and the architectures with circuit level trade-offs in mind.

This dissertation proposes a high performance MIMO receiver design by joint optimization between architectures and algorithms. Firstly, we propose minimum wordlength and precision requirements to ensure negligible performance degradation of several MIMO architectures that include diversity through space-time block codes (STBCs) and detection of spatial multiplexing (SM) using sub-optimal and near-optimal detection algorithms under finite word-length based on results from extensive simulations. We also propose a procedure to quantify the decision-point SNR for MIMO receiver. Secondly, we propose a low latency, low complexity scalable VLSI architecture for QR decomposition, an essential pre-computation for many receiver algorithms, based on modified Gram-Schmidt algorithm.

Lastly, we propose pruned K-Best algorithm for near maximum likelihood (ML) detection of SM scheme. The pruned K-Best algorithm enables a high throughput and low complexity VLSI architectures for SM detection. The proposed architectures for four transmit and four receive SM architectures with 16-QAM requires 13 clock cycles to detect 16 bits and achieves a throughput of 246.15 Mbps and power consumption of 200mW at 75K gates when implemented in 0.18um CMOS process. The proposed architecture is scalable for any QAM constellation and number of transmit antennas. The scalability is shown by extending the architectures to 64-QAM constellation. We conclude this dissertation by describing a comprehensive MIMO receiver design by covering most commonly adopted MIMO architectures.