Abstract

The well-known performance and power bottlenecks in traditional architecture design, in conjunction with the sustained demand for high performance in real world applications, stimulated the creation of new designs that utilize multi-cores in one processor. There are two approaches in multi-core design: homogeneous and heterogeneous. The homogeneous design is based on the replication of simple cores. It is easier for developers to port existing applications to this kind of platform. However, great diversity exists among applications and a homogeneous multi-core chip cannot be optimal for heterogeneous workloads. Therefore, more and more multi-core designs tend to utilize heterogeneous cores and specialized accelerators. The Cell Broadband Engine (CBE) is a representative. Every Cell processor integrates one Power Processing Engine(PPE) core and eight Synergistic Processing Engines (SPE). A PPE core has a traditional memory and cache hierarchy and it accesses memory via caching mechanism. On the other hand, each SPE core only has 256K local storage and accesses its own local storage directly. All data exchange between the SPUs and shared system memory is via high-latency DMA operation.

Therefore, this architecture presents great challenges to programmers who want to utilize parallelism: (1) Threads running on PPE are far different from the ones on SPEs, both in capability and ISAs. The users have to take care of programming threads in each ISA, as well as their cooperation and synchronization. (2) The SPE local storage is so limited that SPE code or data may have to be partitioned into overlay sections. Given the explicit memory hierarchy, it is necessary for the programmers to issue DMA instructions at the appropriate time and transfer them to or from system memory. (3) Shared data in SPE code also needs to be loaded from and stored to main memory. The Cell processor can guarantee the coherence for all DMA transactions. However, the user would have the responsibility to keep data coherence among SPE local storage.

This thesis is inspired by the Open Opell project whose goal is to develop the GNU-Based OpenMP on the CBE platform and address the challenges mentioned above. Our solution involves the whole tool chain and a runtime system. The CBE programmer can take advantage of the convenience of this abstract share-memory programming model. Specifically, we design and implement single source compilation to attack the first challenge. Then the "ghost" mechanism, which invokes overlays and partition manager libraries, helps to deal with the second challenge. Lastly, we try to tackle the third challenge by the software cache library.

In this thesis, we mainly focus on my work in the assembler and linker part of the Open Opell system, which addresses three specific problems: (1) Given a heterogeneous system like CBE, how to support single source compilation? (2) How to design a mechanism to automatically invoke code/data overlays and hide all details to the end-user? (3) How to make the solution and implementation robust and efficient?

The main contributions of this thesis are: (1) We have completed the design of interfaces between different phases in toolchain to support single openMP source program compilation. (2) We have designed the "ghost" mechanism to invoke the overlays and hide the details about the overlay to high-level users. It will work with the partition manager run-time library to complete automatic code/data load if needed. (3) We have implemented the proposed design in our Open Opell system in a robust and efficient manner. We will focus on the assembler and linker implementation in this thesis. We have used a series of experiments with several non-trivial benchmarks to prove our claim.