Abstract

Environments with high levels of ionizing radiation create special design challenges. A single charged particle can knock thousands of electrons loose, causing electronic noise and signal spikes. In the case of digital circuits, this can cause results which are inaccurate or unintelligible. This is a particularly serious problem in the design of artificial satellites, spacecraft, military aircraft, nuclear power stations, and nuclear weapons. In most cases, these high-energy particle strikes do not cause permanent, physical damage to the system; rather they generate correctable, soft errors by causing voltages to flip in the memory cells. This project is focused on designing a radiation-hardened memory system with reasonable tradeoffs in area, power, and performance. Three radiation-hardened methods—Hamming codes, triple mode redundancy, and oversized gates—were applied to provide the most efficient protection. For the memory cell, an all-NMOS design was utilized to save cell area without sacrificing significant access time. By removing the usual separation between PMOS and NMOS, the cell area can decrease by up to 20 percent compared to that of the traditional SRAM and still maintain comparable performance and stability.