Abstract

Multiple core designs have become common place in the processor market, and are hence a major focus in modern computer architecture research. Thus, for both product development and research, multiple core processor simulation environments are necessary. A well-known positive feedback property of computer design is that we use today’s computers to design tomorrow’s. Thus, with the emergence of chip multiprocessors, it is imperative to re-examine simulation environments developed to exploit parallelism.

This thesis is motivated by the increasing difficulty to develop a simple yet accurate and flexible Chip Multiprocessor(CMP) tool for academic research. Using CMP tools developed by other researchers might require a long study phase to understand the tool and at the end of which the tool might not be useful for several reasons such as, inflexibility to add new features, usage of an unknown coding language, issues of portability and nonavailability of extended support for the tool from the developer. Hence we consider that developing a tool suitable for our research needs will provide an excellent foundation for our future work. The tool is also being made available for public use. The tool developed is simple, accurate, flexible(to add new features) and user friendly. We present a programming methodology for directly converting existing uniprocessor simulators into parallelized multiple-core simulators. Our method not only takes significantly less development effort compared to some prior programming techniques, but also possesses advantages by retaining a modular and comprehensible programming structure. Our Chip Multiprocessor(CMP) simulation framework was built on Simplescalar, a simple wide-issue superscalar processor simulator. Our CMP framework has been used for multiple projects and has shown remarkably less time to develop these projects which address issues in relatively diverse topics. It has also been used in EE6304 (a graduate level course for Computer Architecture) and has received good reviews from the students. Researchers from various other research institutions are using this tool for research in the computer architecture field which would further help us to test and verify the tool’s functionality.

This tool developed as a part of this thesis is currently being used by students for developing their projects in HPDC lab at the University of Texas at Dallas. It has also been made public in order to support research on chip multiprocessors at various other academic institutions.

Keywords. Chip Multiprocessors, Simulation Tools, CMP-SIM, chip throughput, Parallel Work Load Tool.