Abstract

High-performance analog-to-digital converters are needed to provide an interface between digital signal processing systems and "real world" analog signals. In many cases, especially in portable applications that use batteries, energy efficiency is of paramount importance and hence low power consumption is critical in this interface.

The pipelined ADC architecture is well suited for many applications due to its ability to provide high throughput at moderately high resolutions. Within this architecture, the residue amplifiers typically determine the converter's overall speed and power performance. This dissertation explores the use of a mixed-signal technique that exploits incomplete settling to relax the speed-noise-linearity trade-off that typically constrains residue amplifiers, thereby reducing the amplifier power consumption by over an order of magnitude.

As a demonstration vehicle, the proposed technique is employed in the first stage of a 12-bit, 75-MS/s proof-of-concept prototype built in a 0.35-μm double-poly, quadruple-metal CMOS process. The prototype demonstrated more than a 60% amplifier power reduction over a previously reported open-loop residue amplifier implementation and achieved more than 90% amplifier power reduction over a conventional op-amp implementation. Furthermore, simulation results show that an implementation of a complete stage in 90-nm CMOS yields even greater savings of over 20 times when compared to the stage power of the proof-of-concept prototype.