Abstract

This dissertation studies the integration of a video compression system on the focal plane. The integration of a video compression circuit and an image sensor on the same chip is expected to improve the performance of the sensor chip and lower fabrication costs. Enabling technologies are researched and a circuit is proposed. The approach followed in this research work was a top-to-bottom approach. The problem was first studied at the system and algorithmic level. Once a system solution was found it was implemented on a silicon chip.

The proposed chip consists of an 80 x 44 active pixel array and a bank of column-level processors that performs the tasks of image decorrelation, quantization, and entropy encoding. The chip provides at its output a compressed bit stream. The integration of all these building blocks was possible due to two key contributions of this dissertation. First, a quantizer and an entropy encoder were combined by noticing that they have common circuitry. The result of exploiting this observation is an analog-to-digital converter capable of performing a joint quantization/coding operation. The second contribution is a low-complexity algorithm that adapts the entropy encoder to the statistics of the image. The chip was fabricated in a 4-metal, 2-poly 0.35-μm complementary metal-oxide-semiconductor (CMOS) process. The chip occupies an area of 2.596 mm x 5.958 mm.

Test and measurement results are presented which verify the validity of the design. The advantages and drawbacks of the proposed implementation are discussed as well. The results of this research work are not limited to the area of focal plane video compression. Other interesting and exciting areas like sensor networks can benefit from this research work.