The IC industry is facing several major barriers at sub-65nm process nodes due to higher levels of integration and physical limitations of the devices. First, power dissipation has significantly increased with increasing clock frequency and higher integration densities. To circumvent this increase in power, we propose several low power design methods at the circuit/system level based on supply/clock gating that target reduction of dynamic, leakage and clock power consumption. Second, intrinsic limitations of the fabrication processes cause fluctuations in device geometries; these translate into variations in circuit parameters (delay, power) leading to manufacturing yield loss. Such issues are further aggravated by the contradictory design requirements of lower power and parametric error resilience. Combating these issues at a single level of abstraction might not be sufficient; hence, innovative and extremely low overhead circuit/architectural co-design techniques are needed to concurrently address these conflicting requirements. Especially, for digital signal processing applications, the "right" tradeoffs between quality and power can prevent parametric failures even under extreme low power operation. In this context, this thesis presents several frequently used DSP core designs where both the low power/error resilience metrics are satisfied. The basic idea behind this design approach is to a) perform sensitivity analysis to determine computations that are critical for maintaining a user-specified output quality, and (b) compute the critical computations with higher priority so that parametric delay errors can affect only the less-critical computations and have minimal effect on output quality. Such quality modulation technique can be effectively utilized for providing increased tolerance to hard faults under a fixed area budget. By providing more redundancy to the critical sections and less redundancy to the less critical ones, we can improve the resiliency of such designs to hard faults as well.
