During fabrication process, mixed analog and digital integrated circuits (ICs) are more susceptible to process variations and physical defects than pure digital ICs. Therefore, it is beneficial to simulate the effects of process variations and defects on mixed-signal designs even before the design goes into production. Simulations of ICs having process variations are performed with Monte Carlo simulations. And, simulations of ICs having physical defects are called fault simulations. However, both simulation schemes require large numbers of instances. Consequently, simulation times can be extremely long, e.g. hours or days. In this System-on-a-Chip (SoC) era, mixed-signal designs are becoming more complex and thus impossible for traditional simulation schemes to be effectively applied.
To dramatically reduce Monte Carlo simulation time and fault simulation time, a new behavioral simulation approach is proposed in this dissertation. Essentially, timing consuming detailed circuit simulations can be replaced by simple linear equations. A flash analog-to-digital converter (ADC) is used here to demonstrate the feasibility of proposed approach. The behavioral models for the flash ADC having process variations and physical defects are built. With these behavioral models, behavioral simulation programs are written in C++ to perform fast Monte Carlo simulations and fault simulations. For the small 3-bit flash ADC, the proposed method reduced the Monte Carlo simulation time, with 30 instances, from 180 hours to a mere 15 minutes. Such dramatic reduction in simulation time was achieved with a maximum prediction error of no more than 6%.
