Network Processors (NPs) are embedded system-on-a-chip multiprocessors that are optimized to perform simple packet processing tasks at data rates of several Gigabits per second. They are the key components to build a performance-scalable and function-flexible network processing system. To meet the performance demands of increasing link speeds and more complex network applications, NPs are implemented with several dozen processor cores and run multiple packet processing applications in parallel. This trend makes it increasingly difficult for application developers to manage and operate the various system resources of NPs for high performance. This dissertation aims at the design methodology for high performance NPs by profiling and mapping applications. The methodology starts with a simple uniprocessor implementation of applications. Through profiling, an architecture-independent representation of the application is developed which exhibits the maximum available parallelism. Using randomized mapping and analytic performance modeling of the network processor system, a static allocation of the workload can be derived. The performance estimation that can be derived from the model allows an optimization of the mapping to maximize throughput performance for any given network processor topology and configuration. The results of this work will enable researchers and engineers to systematically evaluate and quantitatively understand the NPs system issues including application partitioning, architecture organizing, workload mapping and run-time operating. Without this methodology, it will be very difficult if not impossible.
