This dissertation proposes a power-aware SoC design methodology, which is characterized by four key elements. First, SoC infrastructure is developed specifically to create modularity in both the physical floorplan, and application. Second, a statically scheduled interconnect approach eases physical design, limits network overhead, and assures predictable interconnect behavior. This interconnect approach is well suited for signal processing applications critical to portable electronics, including video and speech coding, graphics, and cryptography. Third, system modularity is exploited for power savings by allowing the independent development and use of reconfigurable processing cores. Dynamic parameterization is proposed as a formalism for run-time reconfiguration of these cores. Finally, interconnect behavior monitoring is used to estimate core utilization and control individual voltage and frequency scaling for each core.
This SoC methodology is applied to create and evaluate power-aware infrastructure for the Adaptive System-on-a-Chip (aSoC). Layout level models are implemented to measure performance and verify architectural assumptions. In aSoC the global floorplan is enforced with specific regions and process layers allocated for cores and interconnect. As a result, infrastructure overhead can be less than 5% depending on the granularity of the desired IP cores. Interconnect mesh regularity allows for efficient use of resources as well as providing fast and predictable communication links. This structure allows for the routing of global interconnect, global clock, and multiple supply grids together in the top three layers of metal.
The combination of dynamically parameterized cores and system wide voltage scaling has the potential to reduce power consumption in future SoC devices by more than 90%.
