This dissertation describes a new test generation method in which the test vectors or test sequences are generated based on the pre-determined test profiles. A test profile describes the Boolean function and the minimum test requirement of a cell which may be a gate in a gate level netlist or a VLSI cell from the standard cell library. In a one-time effort, possible faults in each cell are analyzed and simulated in order to establish a set of test requirements. The proposed testing method provides flexibility in dealing with different fault models, such as stuck-at, stuck-open etc., and even the realistic faults by simply changing the contents of test profiles accordingly. Test generation for $I\sb{DDQ}$ testing is also possible using the proposed program. Moreover, this method can also be used to generate the tests for a circuit in a hierarchical fashion and even for the delay faults.
The test generation results running on the MCNC ISCAS85 benchmark circuits show that, for the stuck-at fault model, the proposed program is comparable to Nemesis. Typically, the test sizes are smaller and the test generation times are shorter for most of the benchmark circuits. For the stuck-open fault model, our results are better than that of SOPRANO on the test sizes. In dealing with the bridging faults, the benchmark results show that most of the faults can be detected using the $I\sb{DDQ}$ technique while these faults cannot be detected using the functional test. The results on the MCNC ISCAS85 bench-mark circuits indicate that the proposed method covers almost all functionally detectable realistic faults that include complete breaks and bridging. For the hierarchical test, the results shows that test generation time is shorter for the "hierarchical" circuits while the fault coverage is higher as well. The test generation results based on the delay fault model demonstrate that the delay fault is the most difficult to test for.
